
PIC16F62X
DS40300C-page 92
Preliminary
2003 Microchip Technology Inc.
REGISTER 14-1:
CONFIGURATION WORD
CP1
CP0
CP1
CP0
—
CPD
LVP
BODEN
MCLRE
FOSC2
PWRTE
WDTE
F0SC1
F0SC0
bit 13
bit 0
bit 13-10:
CP1:CP0: Code Protection bits (2)
Code protection for 2K program memory
11
= Program memory code protection off
10
= 0400h-07FFh code protected
01
= 0200h-07FFh code protected
00
= 0000h-07FFhcode protected
Code protection for 1K program memory
11
= Program memory code protection off
10
= Program memory code protection off
01
= 0200h-03FFh code protected
00
= 0000h-03FFh code protected
bit 9:
Unimplemented: Read as ‘0’
bit 8:
CPD: Data Code Protection bit(3)
1
= Data memory code protection off
0
= Data memory code protected
bit 7:
LVP: Low Voltage Programming Enable
1
= RB4/PGM pin has PGM function, low voltage programming enabled
0
= RB4/PGM is digital I/O, HV on MCLR must be used for programming
bit 6:
BODEN: Brown-out Detect Reset Enable bit (1)
1
= BOD Reset enabled
0
= BOD Reset disabled
bit 5:
MCLRE: RA5/MCLR pin function select
1
= RA5/MCLR pin function is MCLR
0
= RA5/MCLR pin function is digital Input, MCLR internally tied to V
DD
bit 3:
PWRTEN: Power-up Timer Enable bit (1)
1
= PWRT disabled
0
= PWRT enabled
bit 2:
WDTEN: Watchdog Timer Enable bit
1
= WDT enabled
0
= WDT disabled
bit 4, 1-0:
FOSC2:FOSC0: Oscillator Selection bits(4)
111
= ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
110
= ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
101
= INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100
= INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011
= EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010
= HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001
= XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000
= LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note
1:
Enabling Brown-out Detect Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Detect Reset is enabled.
2:
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
3:
The entire data EEPROM will be erased when the code protection is turned off.
4:
When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled.
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
x = bit is unknown